The present invention relates to a semiconductor device fabrication method, more specifically a semiconductor device fabrication method which can micronize lines.
As LSI becomes larger-scaled, device micronization is pursued.
In order to realize semiconductor integrated circuits including gate electrodes, lines and contact holes of microdimensions it has been conventionally conducted that the lithography uses short exposure wavelengths for higher resolving ability.
While minimum development dimensions are thus diminished, various device structures which allow alignment margins for alignment between lithography steps have been studied so as to make dimensions of devices smaller without diminishing dimensions of patterns to be formed.
Self-aligned contact (hereinafter called SAC) is noted as a technique that can reduce dimensions of devices without diminishing dimensions of patterns to be formed.
In semiconductor device fabrication methods using SAC, when an inter-layer insulation film 130 is etched, as shown in FIG. 7A, a stopper film 128 functions as the etching stopper, and protects an insulation film 118 from excessive etching, whereby a gate electrode 120 can be prevented from exposure. Even if a disalignment takes place in a lithography step, a contact hole 132 can be formed at a preset position.
However, in the above-described semiconductor device fabrication method, as a pitch between gate electrodes 120 becomes smaller with more micronization of the semiconductor device, as shown in FIG. 7B a stopper film 128 unpreferably defines a small gap 129. As a result, when the inter-layer insulation film 130 is etched with the stopper film 128 as the etching stopper, sometimes that of the inter-layer insulation film 130 in the gap 129 cannot be completely removed.
In such case, in order to remove all the inter-layer insulation film 130 in the gap 129, overetching must be performed. However, the overetching often unpreferably etches not only the inter-layer insulation film 130 but also the stopper film 128 and the insulation film 118, and often unpreferably exposes even the gate electrodes 120 or etches even the silicon substrate 110. This often degrades reliability of the semiconductor device.